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DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
PC1854A
I2C BUS-COMPATIBLE US MTS PROCESSING LSI
The PC1854A is an integrated circuit for US MTS (Multichannel Television Sound) system with the addition of the I2C bus interface. All functions required for US MTS system are incorporated on a single chip. The PC1854A allows users to switch modes and adjust filter and separation circuits through the I2C bus.
FEATURES
* Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, and I2C bus interface incorporated on a single chip * Mode switching and filter/separation adjustments through the I2C bus * Power supply: 8 V to 10 V * On-chip input attenuator for simple interface with intermediate frequency processing IC (I2C bus control) * Output level: 1.4 Vp-p (with L+R signals, 100% modulation)
APPLICATIONS
* TV sets and VCRs for north America
ORDERING INFORMATION
Part Number Package 28-pin plastic SDIP (10.16 mm (400)) 28-pin plastic SOP (9.53 mm (375))
PC1854ACT PC1854AGT
The PC1854A is available only to licensees of THAT Corporation. For information, please call: (508) 229-2500 (U.S.A.), or (03) 5790-5391 (Tokyo).
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12816EJ3V0DS00 (3rd edition) Date Published June 2000 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997
PC1854A
SYSTEM BLOCK DIAGRAM
Tuner
IF processing
C, Y, and deflecting signal processing
Chroma output
CRT
DTS interface
Vertical output
PC1854A
L US MTS processing R Tuning microcontroller SDA Surround signal processing Power amplifier
SCL
Remote controller receive amp.
PIN photodiode
2
Data Sheet S12816EJ3V0DS00
PC1854A
BLOCK DIAGRAM
9V VCC 1 Deemphasis Offset Absorption 28 MOA 1 F + LOT 10 F + ROT 10 F + Pilot Canceller Mode Selector Offset Absorption NOT 10 F + VOA 1 F + WTI 10 F + STI 3.3 F + Timing Current 2fH Trap Spectral RMS Filter
D/A
22 F +
VRE
2
1/2 VCC L-R AM Demodulator L+R LPF Matrix Pilot Discrimination Phase Comparator Stereo VCO
27
PD1 0.1 F PD2
3
26
4 1/4 1/2 ST VCO
25
1 k 4.7 F + +
D1
1 F
5 Stereo Phase Comparator 6
D/A D/A
ST VCO SAP VCO Filter Stereo LPF ST/SAP SW
WideBand VCA WideBand RMS Filter
D/A
24
D2
2.2 F COM + 0.1 F SOA + 0.047 F SDT
23 WideBand RMS 22
7
Input Attenuator
LPF
Filter
fH Trap 8 Offset Absorption Noise BPF SAP BPF
21
ITI 1.6 k 15 k WRB 1 F
9
20 Spectral RMS 19
5.1 k + SRB 3 k dO 1 F + 1 F + DGND
0.47 F +
NDT 68 k SOT
10
Noise Detector
SAP Detector
Phase Detector
11 SAP LPF
Loop Filter
0.1 F External dbx NR SI 12
408 Hz LPF
Variable Emphasis
2.19 kHz LPF
Offset Absorption
18
SAP VCO
D/A
17
ESA
13 1/2 SAP VCO
Filter Adjuster
D/A
16 I2C Bus Interface 15
SCL
AGND
14
SDA
Remark Use the following for external parts. Resistor : Metal film resistor (1 %) for an ITI pin (pin 21). Unless otherwise specified; 5 % Capacitor : Tantalum capacitor (10 %) for STI and WTI pins (pins 22 and 23). Unless otherwise specified; 20 %
Data Sheet S12816EJ3V0DS00
3
PC1854A
PIN CONFIGURATION (Top View)
28-pin plastic SDIP (10.16 mm (400)) * PC1854ACT 28-pin plastic SOP (9.53 mm (375)) * PC1854AGT
Power (9 V) 1/2 VCC Filter Pilot Discrimination Filter 1 Pilot Discrimination Filter 2 Phase Comparator Filter 1 Phase Comparator Filter 2 Composite Signal Input SAP Offset Absorption SAP Discrimination Filter Noise Detection Filter SAP Single Output SAP Single Input External SAP Input Analog GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VCC VRE PD1 PD2
D1 D2
MOA LOT ROT NOT VOA WTI STI ITI WRB SRB dO DGND SCL SDA
28 27 26 25 24 23 22 21 20 19 18 17 16 15
Monaural Offset Absorption L-channel Output R-channel Output Normal Output VCA Offset Absorption Wide-Band RMS Timing Spectral RMS Timing Timing Current Setting Wide-Band RMS Offset Absorption Spectral RMS Offset Absorption Variable Emphasis Offset Absorption Digital GND (for I2C bus) SCL (for I2C bus) SDA (for I2C bus)
COM SOA SDT NDT SOT SI ESA AGND
4
Data Sheet S12816EJ3V0DS00
PC1854A
CONTENTS
1. 2.
PIN EQUIVALENT CIRCUITS .............................................................................................................................. 6 BLOCK FUNCTIONS .......................................................................................................................................... 13 2.1 2.2 2.3 2.4 Stereo Demodulation Block ..................................................................................................................... 14 SAP Demodulation Block ........................................................................................................................ 15 dbx Noise Reduction Block ..................................................................................................................... 16 Matrix Block .............................................................................................................................................. 17
3.
I2C BUS INTERFACE ......................................................................................................................................... 18 3.1 3.2 Data Transfer ........................................................................................................................................... 19 Data Transfer Format .............................................................................................................................. 20
4.
I2C BUS COMMANDS ........................................................................................................................................ 22 4.1 4.2 4.3 4.4 Subaddress List ....................................................................................................................................... 22 Setting Procedure .................................................................................................................................... 23 Explanation of Write Register .................................................................................................................. 25 Explanation of Read Register ................................................................................................................. 28
5.
MODE MATRIX ................................................................................................................................................... 30 5.1 5.2 L-, R-Channel Output (LOT, ROT pins) Matrix ....................................................................................... 30 Normal Output (NOT pin) Matrix ............................................................................................................. 31
6.
USAGE CAUTIONS ............................................................................................................................................ 32 6.1 6.2 6.3 6.4 6.5 6.6 Caution on Shock Noise Reduction ........................................................................................................ 32 Supply Voltage ......................................................................................................................................... 32 Impedance of Input and Output Pins ...................................................................................................... 32 Drive Capability of Output Pins ............................................................................................................... 32 Caution on External Components ........................................................................................................... 33 Change of Electrical Characteristics by External Components ............................................................. 33
7. 8. 9.
ELECTRICAL SPECIFICATIONS ...................................................................................................................... 34 MEASURING CIRCUIT ....................................................................................................................................... 44 PACKAGE DRAWINGS ..................................................................................................................................... 45
10. RECOMMENDED SOLDERING CONDITIONS ................................................................................................ 47
Data Sheet S12816EJ3V0DS00
5
PC1854A
1. PIN EQUIVALENT CIRCUITS (1/7)
Pin No. 1 Power (9 V) Pin Name Symbol VCC Internal Equivalent Circuit
2
1/2 VCC Filter
VRE
VCC 10 k 10 k
5 k 20 k 20 k 10 k
20 k 2
10 k 20 k 5 k GND
3
Pilot Discrimination Filter 1
PD1
VCC 3 15 k 15 k 5 k
4
Pilot Discrimination Filter 2
PD2
1 VCC 2
VCC 15 k 15 k 5 k
4
6
Data Sheet S12816EJ3V0DS00
PC1854A
(2/7)
Pin No. 5 Pin Name Phase Comparator Filter 1 Symbol Internal Equivalent Circuit
D1
VCC 5 15 k 5 k 5 k
6
Phase Comparator Filter 2
D2
1 VCC 2
VCC 15 k 5 k 5 k
6
7
Composite Signal Input
COM
VCC
1 VCC 2
80 k 7 3 k 17 k
5 k
5 k GND
8
SAP Offset Absorption
SOA
VCC 10 k 10 k
5 pF 50 k 3 k
2.3 k
10 k GND 8
Data Sheet S12816EJ3V0DS00
7
PC1854A
(3/7)
Pin No. 9 Pin Name SAP Discrimination Filter Symbol SDT Internal Equivalent Circuit
9 VCC 20 k 10 k
20 k
20 k
10 k GND
10
Noise Detection Filter
NDT
10 VCC 20 k 20 k 20 k
20 k
20 k
20 k
20 k GND
8
Data Sheet S12816EJ3V0DS00
PC1854A
(4/7)
Pin No. 11 Pin Name SAP Single Output Symbol SOT Internal Equivalent Circuit
VCC 2 k
200 11
2 k
GND
12 SAP Single Input SI
1 VCC 2
VCC 10 k 10 k
80 k 5 k 12
5 pF
5 k GND
13
External SAP Input
ESA
1 VCC 2
VCC 10 k 10 k
80 k 5 pF 3 k 13
10 k GND
Data Sheet S12816EJ3V0DS00
9
PC1854A
(5/7)
Pin No. 14 Analog GND Pin Name Symbol AGND Internal Equivalent Circuit
15
SDA (for I2C bus)
SDA
VCC 10 k 10 k 10 k
Note
50 k 5 k 15 30 k 30 k GND
16
SCL (for I2C bus)
SCL
VCC 10 k 10 k 10 k
Note
5 k 16 30 k 30 k GND
17
Digital GND (for I2C bus)
DGND
18
Variable Emphasis Offset Absorption Spectral RMS Offset Absorption
dO
Same as Pin 8
19
SRB
5 k 5 k
VCC 5 k
3 k
3 k 19 3 k
5 k GND
Note No protection diode is provided on the VCC side so that the I2C bus line is not pulled to 0 V when the power is OFF (VCC = 0 V).
10
Data Sheet S12816EJ3V0DS00
PC1854A
(6/7)
Pin No. 20 Pin Name Wide-Band RMS Offset Absorption Symbol WRB Same as pin 19 Internal Equivalent Circuit
21
Timing Current Setting
ITI
VCC 10 k 10 k
5 k 20 pF
10 k
10 k
10 k
10 k
21 30 k GND
22
Spectral RMS Timing
STI VCC 5 k 600
5 k
5 k 5 k
22 5 k GND
23
Wide-Band RMS Timing
WTI
Same as pin 22
24
VCA Offset Absorption
VOA
Same as pin 8
Data Sheet S12816EJ3V0DS00
11
PC1854A
(7/7)
Pin No. 25 Pin Name Normal Output Symbol NOT Internal Equivalent Circuit
VCC 1 k 10 k
200 25 200 5 k
1 k 5 k GND
26
R-channel Output
ROT
Same as pin 25
27
L-channel Output
LOT
28
Monaural Offset Absorption
MOA
Same as pin 8
12
Data Sheet S12816EJ3V0DS00
PC1854A
2. BLOCK FUNCTIONS
In the US, TV audio signals are broadcast in FM modulation. The stereo (L-R), Sub Audio Program (SAP) and telemetry signals are multiplexed in a higher frequency band than the monaural (L+R) signal (50 Hz to 15 kHz). The US MTS system base-band spectrum is described before: Figure 2-1. US MTS System Base-Band Spectrum
50
Stereo signal (L-R)
Audio carrier deviation (kHz)
Stereo pilot signal
Monaural signal (L+R) 25
15
Sub Audio Program (SAP) signal
5 3 0 fH (15.734 kHz) 2 fH 3 fH 4 fH 5 fH 6 fH
Telemetry signal 6.5 fH
Modulation frequency (Hz)
Table 2-1. US MTS System Base-Band Spectrum
Maximum audio carrier deviation (kHz) 25 Only stereo broadcasting AM modulation (carrier frequency 2 fH), dbx noise reduction processing FM modulation (carrier frequency 5 fH), maximum frequency deviation 10 kHz) dbx noise reduction processing FM modulation (carrier frequency 6.5 fH maximum frequency deviation 3 kHz) 5 50 15
Signal frequency band Monaural signal (L+R) Stereo pilot signal Stereo signal (L-R) Sub Audio Program (SAP) signal Telemetry signal Audio Data 50 Hz to 15 kHz 15.734 kHz 50 Hz to 15 kHz 50 Hz to 10 kHz
Signal processing system
0 to 3.4 kHz 0 to 1.5 kHz
3
Data Sheet S12816EJ3V0DS00
13
PC1854A
2.1 Stereo Demodulation Block (1) Stereo LPF This filter eliminates signals in the vicinity of 5 fH to 6 fH, such as SAP (Sub Audio Program) (5 fH) and telemetry signals (6.5 fH) . The PC1854A's internal L-R demodulator, which uses a double-balanced circuit, demodulates L-R signals by multiplication of the L-R signal with the signal at the L-R carrier frequency (2 fH). The L- R signal tends to receive interference from the 6 fH signal because a square waveform is used as the switching carrier in this method. To eliminate this interference, the PC1854A incorporates traps at 5 fH and 6 fH. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5). (2) Stereo phase comparator The 8 fH signal generated at the stereo VCO is divided by 8 (4 x 2) and then multiplied by the pilot signal passed through the stereo LPF. The two signals differ from each other by 90 degrees in terms of phase. The resistor and capacitor connected to Pins D1 and D2 form a filter that smooths the phase error signal output from the stereo phase comparator, converting the error signal to the DC voltage. When the voltage difference between pins D1 and D2 becomes 0 V (strictly speaking, not 0 V by the internal offset voltage), the VCO runs at 8 fH. The lag/lead filter externally connected to the pins D1 and D2 determines the capture range. (3) Stereo VCO The VCO runs at 8 fH with the internal capacitor. The frequency is adjusted by setting the Stereo VCO setting bits (write register, subaddress 01H, bits D0 to D5). (4) Divider (Flip-flop) Produces two separate fH signals: the inphase fH signal, and the fH signal differing by 90 degrees from the input pilot signal by dividing the 8 fH frequency from the stereo VCO by 8 (4 x 2). (5) Pilot discrimination phase comparator (Level detector) Multiplies the pilot signal from the COM pin with the inphase fH signal from the divider. The resulting signal is smoothed by passing it through the external filter connected to the PD1 and PD2 pins and converted into DC voltage value that is used to determine whether or not a stereo pilot signal (read register, bit D6) is present. (6) Pilot canceler The fH signal from the divider is added to the stereo signal in resistor matrix depending on the level of the input pilot signal to cancel the pilot signal. (7) L+R LPF This LPF which has traps at fH and 24 kHz, allows only the monaural signal to pass through. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5). (8) De-emphasis The filter is a 75-s de-emphasis filter for the monaural signal. The response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5). (9) L-R AM demodulator Demodulates the L-R AM-DSB modulated signal by multiplying with the 2fH signal which is synchronized to the pilot signal. The 2-fH square wave is used as the switching carrier.
14
Data Sheet S12816EJ3V0DS00
PC1854A
2.2 SAP Demodulation Block (1) SAP BPF Picks up the SAP signal by the 50-kHz and 102-kHz traps and a response peak at 5 fH. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5). (2) Noise BPF The PC1854A monitors signals picked up by the noise band-pass filter (fO 180 kHz), and distinguishes noise from signals. By this method, the PC1854A prevents faulty SAP detection in a weak electric field. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5). (3) Noise detector Performs full-wave rectification of noise from noise band-pass filter, changes it to the DC voltage, and inputs it to the comparator. When the noise level exceeds the reference level, the detector recognizes noise, and the noise detection bit (read register, bit D4) is set "1". The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor connected to the NDT. (4) SAP detector Detects the signal from the SAP band-pass filter and smooths it through the SDT pin and inputs it to the comparator. When the SAP signal is detected, the SAP signal bit (read register, bit D5) is set "1". (5) SAP demodulation circuit The SAP demodulator consists of a phase detector, a loop filter and an SAP VCO (PLL detection circuit). The SAP VCO oscillates at 10 fH, and performs phase comparison between the signal divided by 2 of the VCO frequency and the SAP signal to make the PLL. The SAP VCO oscillating frequency is adjusted by setting the SAP VCO setting bits (write register, subaddress 05H, bits D0 to D5). (6) SAP LPF Eliminates the SAP carrier and high-frequency buzz. The filter consists of a 2nd-order low-pass filter and fH trap filter. The filter response is adjusted by setting the Filter setting bits (write register, subaddress 02H, bits D0 to D5).
Data Sheet S12816EJ3V0DS00
15
PC1854A
2.3 dbx Noise Reduction Block All the filters required for TV-dbx noise reduction are incorporated. The response to these filters is adjusted by setting all the Filter setting bits (write register, subaddress 02H, bits D0 to D5). (1) LPF This LPF has traps at fH and 24 kHz each. The fH trap filter minimizes interference by the fH signal which is not synchronized with the pilot signal (for example, leakage of the synchronous idle and buzz from the video signal). (2) 408-Hz LPF This filter is a de-emphasis filter. Its transfer function is as follows: f 5.23k f 408
1+j T(f) = 1+j
(3) Variable emphasis Also called the spectral VCA. It is controlled by the spectral RMS. The transfer function is as follows: f 20.1k f 20.1k 1 + 51b b+1 1 + 51 b+1
1+j S-1 (f, b) = 1+j
x x
where "b" is the variable transferred from the spectral RMS for controlling. (4) Wide-band VCA A VCA whose operating frequency range is mainly low to mid frequencies and controlled by the wide-band RMS. The transfer function is as follows: W-1 (a) = a where "a" is the variable transferred from the wide-band RMS for controlling. (5) 2.19-kHz LPF This filter is a de-emphasis filter. Its transfer function is as follows: f 62.5k f 2.19k
1+j T(f) = 1+j
16
Data Sheet S12816EJ3V0DS00
PC1854A
(6) Spectral RMS filter A filter that limits the band width of the signal input to the RMS which controls the variable emphasis. The transfer function is as follows: f 7.66k f 3.92k f 3.92k
(j T (f) = 1+j f
)2 f 7.66k x )2
j
7.31k
+ (j
1+j
(7) Wide-band RMS filter A filter that limits the band width of the signal input to the wide-band RMS which controls the wide-band VCA. The transfer function is as follows: 1 1+j f 2.09k
T(f) =
(8) Spectral RMS Detects the RMS value of the signal passed through the spectral RMS filter, and converts the signal to the DC voltage. The release time is set by adjusting the current IT of the PC1854A and the capacitance of the external capacitor connected to the STI pin. The current IT is set by the current value output from the ITI pin. (9) Wide-band RMS Detects the RMS value of the signal passed through the wide-band RMS filter, and converts the signal to the DC voltage. The release time is set by adjusting the current IT of the PC1854A and the capacitance of the external capacitor connected to the WTI pin. The current IT is set by the current value output from the ITI pin.
2.4 Matrix Block (1) Matrix Adds L+R signal and L-R signal to output L signal, and subtracts L+R signal from L-R signal to output R signal. (2) Mode selector Selects the user-selected mode among the monaural, stereo, SAP, external SAP input signals, and mute, then outputs it from the NOT, ROT and LOT pins.
Data Sheet S12816EJ3V0DS00
17
PC1854A
3. I2C BUS INTERFACE
The PC1854A uses the I2C bus interface that is developed by Philips. The serial clock line (SCL) and serial data line (SDA) employ the 2-wire configuration as shown in Figure 3-1. The PC1854A contains seven (1 byte 8 bits) write registers and one read register through the I2C bus interface circuit. Serial Clock Line (SCL) The master CPU outputs a serial clock to achieve data synchronization. The PC1854A receives serial data based on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz. Serial Data Line (SDA) The master CPU outputs data synchronously with the serial clock. The PC1854A receives this data based on the serial clock. The input level is CMOS-compatible. Figure 3-1. Internal Equivalent Circuit of Interface Pins
RP SCL SDA
RP
PC1854A
No protection diode is provided on the VCC side for the SCL and SDA pins so that the I2C bus line is not pulled to 0 V when the power is OFF (VCC = 0 V).
18
Data Sheet S12816EJ3V0DS00
PC1854A
3.1 Data Transfer (1) Start condition The start condition is created when SDA changes from high to low while SCL is high, as shown in Figure 3-2. When the PC1854A receives this information, it captures data sent in synchronization with the clock. (2) Stop condition The stop condition is created when SDA changes from low to high while SCL is high, as shown in Figure 3-2. When the PC1854A receives this information, it stops receiving or outputting data. Figure 3-2. Data Transfer Start/Stop Condition
3.5 V SDA 1.5 V 4.0 s MIN. 3.5 V SCL 1.5 V 4.7 s MIN.
Start
Stop
(3) Data transfer When transferring data, be sure to switch data only when SCL is low, as shown in Figure 3-3. When SCL is high, the data must not be changed. Figure 3-3. Data Transfer
SDA
Note 1 Note 2
SCL
Note 3
Note 4
Notes 1. Data hold time: 300 ns MIN. 2. Data setup time: 250 ns MIN. 3. Interval when data cannot be changed 4. Interval when data can be changed
Data Sheet S12816EJ3V0DS00
19
PC1854A
3.2 Data Transfer Format An example of data transfer in the write mode is shown in Figure 3-4. Figure 3-4. Data Transfer Example in Write Mode
SDA
D6 D5 D4 D3 D2 D1 D0
Write mode
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SCL
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
Start
Slave address
Read/ Write Acknowledge
Subaddress
Acknowledge
data
Acknow- Stop ledge
Data consists of 8-bit units. This 8-bit data must always be followed by an acknowledge bit. Data transfer must be done on an MSB-first basis. The first byte after a start condition specifies the slave address. The slave address consists of 7 bits. Table 3-1 shows the slave addresses of the PC1854A. These slave addresses are registered by Philips. Table 3-1. Slave Addresses of PC1854A
Slave address Mode Write Read 1 1 0 0 0 0 0 0 1 1 1 1 1 1 0 1
D6
D5
D4
D3
D2
D1
D0
Read/Write
The bit following the slave address is the read/write bit specifying the direction of the data to be transferred. During the read operation, data is transferred from the PC1854A to the master CPU. During the write operation, data is transferred from the master CPU to the PC1854A. "0" and "1" are written to the Read/Write bit during the Write and Read modes, respectively. The byte following the slave address is the subaddress of the PC1854A in the write mode. The PC1854A has seven subaddresses, SA0 to SA6, which are made up of 8 bits. Following the subaddress byte is the data to be set to the subaddress.
20
Data Sheet S12816EJ3V0DS00
PC1854A
(1) 1-byte data transfer The format for 1-byte data transfer is the following:
Slave address Write Acknow Acknow Subaddress mode -ledge -ledge Acknow Stop -ledge
Start
Data
(2) Continuous data transfer The format when transferring multiple (7) bytes of data at one time is the following:
Start Slave address Write Acknow Acknow Subaddress mode -ledge -ledge Data1 Acknow -ledge Data2 Acknow -ledge Data7 Acknow Stop -ledge
The master CPU transfers "00H" as subaddress SA0 following the start condition and slave address. After the subaddress SA0, the master CPU transfers the SA0 data, and continues with SA1, SA2, ..., SA6 data without transferring stop conditions in between. The subaddress is automatically incremented. Finally, the stop condition is transferred and the transfer is completed. (3) Data read The PC1854A has one read register. The contents of this register can be read by the master CPU. The format when data is read is the following:
Slave address Acknow -ledge Nonacknow Stop -ledge
Start
Read
Data
(4) Acknowledge In the case of the I2C bus, an acknowledge bit is added to the data as the 9th bit to determine whether data transfer was successful. The master determines the success or failure of data transfer based on whether this acknowledge bit is a logical low or high. If the acknowledge interval is a logical low, this indicates that data transfer was successful. If it is a logical high, this indicates that data transfer was unsuccessful or that the slave side forcibly released the bus as a non-acknowledge state.
Data Sheet S12816EJ3V0DS00
21
PC1854A
4. I2C BUS COMMANDS
4.1 Subaddress List (1) Write register (command list)
Subaddress 00H MSB D7 0 LSB D0
D6 During noise detection Stereo/SAP output stop 0: SAP OFF 1: Stereo, SAP OFF fH monitor ON/OFF 0: OFF 1: ON Pilot canceler ON/OFF 0: ON 1: OFF 0 0 5 fH monitor ON/OFF 0: OFF 1: ON 0
D5
D4
D3
D2
D1
Input level setting
01H
0
Stereo VCO setting
02H
0
Filter setting
03H 04H 05H
0 0 0
Low-band separation setting High-band separation setting SAP VCO setting
06H
0
Normal track Normal track SAP1/SAP2 output select 1 output select 2 switchNote 0: SAP 0: SAP 0: SAP1 1: External SAP 1: Monaural 1: SAP2
Stereo/SAP switch 0: Stereo 1: SAP
Forced monaural Mute ON/OFF ON/OFF 0: OFF 0: ON 1: ON 1: OFF
Note Output when SAP1 or SAP2 is selected is as follows:
LOT pin (L-channel output) SAP1 SAP2 Monaural (L+R) SAP SAP ROT pin (R-channel output)
Remark The initial value of write register after power-on reset * Mute register (subaddress 06H, bit D0) = 0 (Mute: ON) * Other registers = undefined (setting properly after power-on reset) (2) Read register
MSB D7 LSB D0 1
D6
D5
D4
D3
D2
D1 1
Power-on reset Broadcast status Noise detection Reception status 1: Detection 0: Not available Stereo broadcast SAP broadcast Stereo pilot SAP signal 0: Not available 0: Not available 1: Available reception reception 1: Available 1: Available 0: Not available 0: Not available 1: Available 1: Available
22
Data Sheet S12816EJ3V0DS00
PC1854A
4.2 Setting Procedure Precise adjustment of the dbx decoder is absolutely critical for optimum performance. Where possible, the adjustment should be performed after the PC1854A is mounted on the chassis and with the video system active. Set the data of write register as follows before the adjustment, because the registers other than the Mute register are defined. Table 4-1. Default Setting of Write Register
Bit Subaddress 00H 01H 02H 03H 04H 05H 06H
D7 0 0 0 0 0 0 0
D6 0 0 0 0 0 0 0
D5 1 1 1 1 1 1 0
D4 0 0 1 0 0 0 0
D3 0 0 1 0 0 0 0
D2 0 0 1 0 0 0 0
D1 0 0 1 0 0 0 0
D0 0 0 1 0 0 0 1
(1) Input level setting (write register, subaddress 00H, bits D5 to D0) <1> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <2> Input sine wave of 300 Hz, 150 mVrms to COM pin. <3> Set bits D5 to D0 (Input level setting bits) of subaddress 00H so that the output level of ROT pin is 500 mVrms (10 mVrms). (2) Stereo VCO setting (write register, subaddress 01H, bits D6 to D0) Perform this adjustment with no signal applied. <1> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <2> Write "1" to bit D6 (fH monitor: ON) of subaddress 01H. <3> Connect frequency counter to ROT pin, and set bits D5 to D0 (Stereo VCO setting bits) of subaddress 01H so that frequency counter displays 15.73 kHz (0.1 kHz). <4> When setting is completed, write "0" to bit D6 (fH monitor: OFF) of subaddress 01H. (3) Filter setting (write register, subaddress 02H, bits D6 to D0) <1> Write "1" to bit D6 (Pilot canceler: OFF) of subaddress 02H. <2> Input pilot signal (15.734 kHz, 30 mVrms or higherNote) to COM pin and set data of bits D5 to D0 (Filter setting bits) of subaddress 02H so that the output level of the ROT pin becomes as small as possible (Decrease the set data from 63 (decimal)). <3> When setting is completed, write "0" to bit D6 (Pilot canceler: ON) of subaddress 02H. Note 100 mVrms is recommended.
Data Sheet S12816EJ3V0DS00
23
PC1854A
(4) Separation setting (write register, subaddresses 03H and 04H, bits D5 to D0) <1> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <2> Write "20H" to bits D5 to D0 (High-band separation setting bits) of subaddress 04H. <3> Input composite signal to COM pin (300 Hz, 30% modulation, L-only, with noise reduction), and set bits D5 to D0 (Low-band separation setting bits) of subaddress 03H so that the output level of the ROT pin is as small as possible. <4> Change the modulation frequency of the composite signal to 3 kHz, and set bits D5 to D0 of subaddress 04H so that the output level of the ROT pin is as small as possible. <5> While bits D5 to D0 of subaddress 04H are set as in step <4> above, repeat the setting procedure of step <3> for bits D5 to D0 of subaddress 03H. (5) SAP VCO setting (write register, subaddress 05H, bits D6 to D0) Perform this adjustment with no signal applied. <1> Add a 1 M resistor between the SOA pin and GND. <2> Write "1" to bit D0 (Mute: OFF) of subaddress 06H. <3> Write "1" to bit D6 (5 fH monitor: ON) of subaddress 05H. <4> Connect a frequency counter to the ROT pin, and set bits D5 to D0 of subaddress 05H (SAP VCO setting bits) so that 78.67 kHz (0.5 kHz) is displayed on the frequency counter. <5> When setting is completed, write "0" to bit D6 (5 fH monitor: OFF) of subaddress 05H. <6> Delete the 1 M resistor between the SOA pin and GND.
24
Data Sheet S12816EJ3V0DS00
PC1854A
4.3 Explanation of Write Register (1) Stereo/SAP output stop function during noise detection Stereo/SAP output stop can be selected with the data of bit D6 of subaddress 00H during weak electrical field conditions (noise level during recommended circuit use is 30 mVrms (TYP.) or more). SAP output stop : Only SAP output is stopped.
SAP and stereo output stop : SAP and stereo outputs are stopped, switch to monaural output. Noise level detection is performed, when detected a noise about 11.5 fH (180 kHz), a frequency that is sufficiently apart from that of the high frequency signals such as the stereo, SAP, and telemetry signal. If noise is detected, "1" is set to bit D4 of the read register (Refer to section 4.4 (4) Noise detection). Figure 4-1. Stereo/SAP Output Stop Function during Noise Detection
D7 00H 0 D6 During noise detection D5 D4 D3 D2 D1 D0
Input level setting
Stereo/SAP output stop function during noise detection 0 1 SAP output stop SAP and stereo output stop
(2) Mute The mute function can be set ON/OFF with the data of bit D0 of subaddress 06H. The mute on state is entered when bit D0 is set to 0 after power-on reset. Figure 4-2. Mute
D7 06H 0 D6 0 D5 Normal track output select 1 D4 Normal track output select 2 D3 SAP1/SAP2 switch D2 Stereo/SAP switch D1 Forced monaural ON/OFF D0 Mute ON/OFF
Mute 0 Mute ON 1 Mute OFF
Caution
When switching the power ON/OFF, use the mute function (200 ms) outside the PC1854A in order to minimize shock noise.
Data Sheet S12816EJ3V0DS00
25
PC1854A
(3) Mode switch (L-, R-channel output (LOT, ROT pins)) The signal to be output can be selected from the L- and R-channel outputs (LOT, ROT pins) with bits D3 to D1 of subaddress 06H. For the combinations of bit and output signal, refer to section 5.1 L-, R-Channel Output (LOT, ROT pins) Matrix. Forced monaural ON/OFF : When set to ON, a monaural signal is forcibly output regardless of the selection of other bits. Stereo/SAP switch SAP1/SAP2 switch : When forced monaural is set to OFF, performs selection of stereo or SAP. : When SAP output is selected with the stereo/SAP switch, performs selection of SAP1 or SAP2.
L-Channel Output (LOT pin) SAP1 SAP2 Monaural (L+R) output R-Channel Output (ROT pin)
SAP output SAP output
Figure 4-3. Mode Switch (L-, R-Channel Output (LOT, ROT pins))
D7 06H 0 D6 0 D5 Normal track output select 1 D4 Normal track output select 2 D3 SAP1/SAP2 switch D2 Stereo/SAP switch D1 D0
Forced monaural Mute ON/OFF ON/OFF
Forced monaural 0 Forced monaural OFF 1 Forced monaural ON
Stereo/SAP switch 0 1 Stereo output SAP output
SAP1/SAP2 switch 0 1 SAP1 output SAP2 output
26
Data Sheet S12816EJ3V0DS00
PC1854A
(4) Mode switch (normal signal output (NOT pin)) The signal output from the normal signal output (NOT pin) can be selected with bits D5 to D1 of subaddress 06H. For the combinations of bit and output signal, refer to section 5.2 Normal Output (NOT pin) Matrix. Normal track output select 2 : Selects SAP or monaural signal. Normal track output select 1 : Selects SAP signal or external SAP signal. Forced monaural ON/OFF Stereo/SAP switch : When ON is selected, monaural signal is forcibly output regardless of stereo/SAP switch selection. : Selects SAP or stereo signal when other switches are selected as follows; Normal track output select 1: SAP Normal track output select 2: SAP Forced monaural: OFF Figure 4-4. Mode Switch (Normal Signal Output (NOT Pin))
D7 06H 0 D6 0 D5 Normal track output select 1 D4 Normal track output select 2 D3 SAP1/SAP2 switch D2 Stereo/SAP switch D1 D0
Forced monaural Mute ON/OFF ON/OFF
Forced monaural 0 Forced monaural OFF 1 Forced monaural ON
Stereo/SAP switch 0 1 Stereo output SAP output
Normal track output select 2 0 1 SAP output Monaural output
Normal track output select 1 0 1 SAP output External SAP output
Data Sheet S12816EJ3V0DS00
27
PC1854A
4.4 Explanation of Read Register (1) Power-on reset detection Whether a power-on reset was detected is detected with bit D7 of the read register. Figure 4-5. Power-On Reset Detection
D7 Power-on reset Stereo pilot SAP signal D6 D5 D4 D3 D2 D1 D0
Broadcast status Noise detection
Reception status Stereo broadcast reception SAP broadcast reception 1 1
Power-on reset detection 1 Power-on reset detection
(2) Stereo, SAP broadcast (broadcast status) detection Whether SAP or stereo broadcast from a broadcasting station is being broadcast is detected with bits D5 and D6 of the read register. When a SAP signal (5 fH) or stereo pilot signal is detected, the register data becomes "1". Figure 4-6. Stereo, SAP Broadcast (Broadcast Status) Detection
D7 Power-on reset Stereo pilot SAP signal D6 D5 D4 D3 D2 D1 D0
Broadcast status Noise detection
Reception status Stereo broadcast reception SAP broadcast reception 1 1
SAP signal 0 1 No SAP broadcast SAP broadcast (SAP signal detected)
Stereo pilot 0 1 No Stereo broadcast Stereo broadcast (stereo pilot signal detected)
28
Data Sheet S12816EJ3V0DS00
PC1854A
(3) Stereo, SAP broadcast reception (reception status) detection Whether SAP or stereo broadcast is being received and the PC1854A outputs the audio signal can be detected with bits D2 and D3 of the read register. The register data become "1" only if the SAP signal (5 fH) is detected when the SAP broadcast reception is selected, or if the stereo pilot signal is detected when the stereo broadcast reception is selected. Figure 4-7. Stereo, SAP Broadcast Reception (Reception Status) Detection
D7 Power-on reset Stereo pilot SAP signal D6 D5 D4 D3 D2 D1 D0
Broadcast status Noise detection
Reception status Stereo broadcast reception SAP broadcast reception 1 1
SAP broadcast reception 0 1 No outputting SAP broadcast Outputting SAP broadcast
Stereo broadcast reception 0 1 No outputting stereo broadcast Outputting stereo broadcast
(4) Noise detection Noise can be detected with bit D4 of the read register. It is monitored in the vicinity of the 11.5 fH (180 kHz) signal level and noise is detected. During noise detection, the operation of the SAP demodulator block and the stereo demodulation block is interrupted (Refer to section 4.3 (1) Stereo/SAP output stop function during noise detection). Figure 4-8. Noise Detection
D7 Power-on reset Stereo pilot SAP signal D6 D5 D4 D3 D2 D1 D0
Broadcast status Noise detection
Reception status Stereo broadcast reception SAP broadcast reception 1 1
Noise detection 0 1 No noise Noise
Data Sheet S12816EJ3V0DS00
29
PC1854A
5. MODE MATRIX
5.1 L-, R-Channel Output (LOT, ROT pins) Matrix Mute OFF (Write register, subaddress 06H, bit D0 : "1") (1) Read register, bit D4: 0
Broadcast mode Write Register Forced Stereo/SAP SAP1/SAP2 monaural switch switch ON/OFF Subaddress 06H Bit D1 Monaural Stereo -- 0 1 Monaural + SAP 0 0 1 -- 0 1 1 Stereo + SAP 0 -- 0 1 -- -- 0 1 1 -- -- L+R L+R -- L SAP SAP 0 L+R L+R R 1 1 1 0 -- Bit D2 -- -- Bit D3 -- -- Stereo/SAP output stop Output L-ch output (LOT) R-ch output (ROT) Read Register Broadcast status Stereo pilot SAP signal Reception status Stereo SAP broadcast broadcast reception reception Bit D3 0 1 0 0 1 0 0 1 SAP 0 0 1 Bit D2 0 0
Subaddress 00H Bit D6 -- -- L L+R L+R SAP L+R R Bit D6 0 1 Bit D5 0 0
(2) Read register, bit D4: 1
Broadcast mode Write Register Forced Stereo/SAP SAP1/SAP2 monaural switch switch ON/OFF Subaddress 06H Bit D1 Monaural Stereo -- 0 Bit D2 -- -- Bit D3 -- -- Stereo/SAP output stop Output L-ch output (LOT) R-ch output (ROT) Read Register Broadcast status Stereo pilot SAP signal Reception status Stereo SAP broadcast broadcast reception reception Bit D3 0 1 0 0 0 0 Bit D2 0 0
Subaddress 00H Bit D6 -- 0 1 L L+R L+R L+R R Bit D6 0 1 0 0 Bit D5 0 0
Monaural + SAP
0
1
0
0 1
1
0 1
Stereo + SAP
0
0
--
0 1
L L+R
R
1 0
0
1 0
0
1
0
0 1
1
0 1
Remarks 1. When the PC1854A recognizes a weak electric field, bit D4 of the read register becomes "1". 2. -- : Don't care.
30
Data Sheet S12816EJ3V0DS00
PC1854A
5.2 Normal Output (NOT pin) Matrix Mute OFF (Write register, subaddress 06H, bit D0 : "1")
Broadcast mode Write Register Normal track output select 2 Normal track output select 1 Forced monaural ON/OFF Subaddress : 06H Bit: D4 Monaural Stereo Monaural + SAP -- -- 0 Bit: D5 -- -- 0 Bit: D1 -- -- 0 Bit: D2 -- -- 0 1 1 1 1 Stereo + SAP 0 -- 0 0 0 1 1 1 1 -- -- -- -- -- -- -- Bit: D3 -- -- -- L+R L+R L+R SAP L+R External SAPNote L+R L+R SAP L+R External SAPNote L+R Stereo /SAP switch SAP1/SAP2 switch Output Normal output (NOT pin)
Note SAP signal input from ESA pin. Remark -- : Don't care. Caution All normal outputs with weak electric field are L+R.
Data Sheet S12816EJ3V0DS00
31
PC1854A
6. USAGE CAUTIONS
6.1 Caution on Shock Noise Reduction When switching the power ON/OFF, use the mute function (approx. 200 ms) outside the PC1854A in order to minimize shock noise.
6.2 Supply Voltage Pass data through the I2C bus only after stabilizing the supply voltage of the entire application system.
6.3 Impedance of Input and Output Pins Table 6-1. Impedance of Input and Output Pins
Input pin Symbol COM SI ESA Description Composite signal input SAP single input External SAP input Impedance 80 k Symbol SOT NOT ROT LOT Output pin Description SAP single output Normal output R-channel output L-channel output Impedance 360 15
6.4 Drive Capability of Output Pins Table 6-2. Drive Capability of Output Pins
Pin symbol SOT NOT ROT LOT Pin description SAP single output Normal output R-channel output L-channel output Output pin-GND Connection Resistance 10 k Drive capability 3-k load or less 700- load or less
Remark If the load capacitance of the output pins (SOT, NOT, ROT, LOT pins) exceeds 100 pF, parasitic oscillation may occur. In this case, connect a resistor between the output pins and the load capacitance. Bear in mind that the load capacitance is changed by wiring pattern on the printed circuit board.
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Data Sheet S12816EJ3V0DS00
PC1854A
6.5 Caution on External Components According to the license contract with THAT Corporation, use the following for external components. With regard to the use of other external components, please contact to THAT Corporation. Table 6-3. External Components
Pin symbol ITI STI WTI Pin description Timing current setting Spectral RMS timing Wide-band RMS timing External component Metal film resistor (1 %) Tantalum capacitor (10 %)
6.6 Change of Electrical Characteristics by External Components (1) SAP sensitivity can be lowered by inserting a resistor between the SDT pin and GND. (2) Noise sensitivity can be changed by changing the value of the resistor between the NDT pin and GND. (3) The capture range can be changed by changing the recommended 1 F value of the capacitor between the D1 and D2 pins (Refer to BLOCK DIAGRAM). Reducing the capacitor value increases the capture range, and increasing it reduces the capture range. However, too small a capacitor value may cause the distortion rate to become worse during stereo output, or may cause malfunction. In this case, please contact NEC.
Data Sheet S12816EJ3V0DS00
33
PC1854A
7. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (Unless otherwise specified, TA = +25C)
Parameter Power supply voltage I 2C bus input pin voltage Symbol VCC Vcont Vin PD To SDA, SCL pins COM pin TA = 75 C Conditions Ratings 11 VCC VCC Unit V V V mW mW C C
Composite signal input voltage Power dissipation
PC1854ACT (SDIP) PC1854AGT (SOP)
600 340 -20 to +75 -40 to +125
Operating ambient temperature Storage temperature
TA Tstg
VCC = 9 V
Caution
If any of the parameters exceeds the absolute maximum ratings, even momentarily, the device reliability may be impaired. The absolute maximum ratings are values that may physically damage the product. Be sure to use the product within the ratings.
Recommended Operating Range (Unless otherwise specified, TA = +25C)
Parameter Power supply voltage Output load impedance 1 Symbol VCC RL1 AC load impedance that can be driven by outputs of NOT, ROT and LOT pins (at 100% modulation) AC load impedance that can be driven by output of SOT pin (at 100% modulation) Signal voltage to COM pin L+R signal (100% modulation) L-R signal (100% modulation) Pilot signal SAP signal I2C bus input pin voltage (High) I 2C bus input pin voltage (Low) VcontH VcontL fSCL SCL pin SDA, SCL pins 3.5 0.0 Conditions MIN. 8.0 2 TYP. 9.0 MAX. 10.0 Unit V k
Output load impedance 2
RL2
10
k
Signal input voltage
Vin
0.424 0.848 0.0848 0.254 5.0 0.0 5.0 1.5 100
Vp-p Vp-p Vp-p Vp-p V V kHz
Clock frequency
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Data Sheet S12816EJ3V0DS00
PC1854A
Electrical Characteristics (unless otherwise specified, TA = 25C, RH 70 %, VCC = 9.0 V) (1/2)
Parameter Supply current Stereo detection input sensitivity Stereo detection hysteresis Stereo detection capture range Symbol ICC STSENCE STHY STCCL STCCH SAP detection input sensitivity SAP detection hysteresis Noise detection input sensitivity Noise detection hysteresis Monaural total output voltage Stereo total output voltage SAP total output voltage SAP single output voltage Normal output voltage Difference between monaural L and R output voltage SAPSENCE SAPHY NOSENCE NOHY VOMO VOST VOSAP1 VOSAP2 VONO VOLR 300 Hz, 100% modulation Noise reduction: OFF 300 Hz, 100% modulation Monaural signal 300 Hz, 100% modulation 1 kHz, 30% modulation (300 Hz: 0 dB) 3 kHz, 30% modulation (300 Hz: 0 dB) 8 kHz, 30% modulation (300 Hz: 0 dB) 12 kHz, 30% modulation (300 Hz: 0 dB) 1 kHz, 30% modulation (300 Hz: 0 dB) 3 kHz, 30% modulation (300 Hz: 0 dB) 8 kHz, 30% modulation (300 Hz: 0 dB) 12 kHz, 30% modulation (300 Hz: 0 dB) 1 kHz, 30% modulation (300 Hz: 0 dB) 3 kHz, 30% modulation (300 Hz: 0 dB) 8 kHz, 30% modulation (300 Hz: 0 dB) No signal 15.734 kHz, sine wave Only stereo pilot signal input Vin = 30 mVrms Only stereo pilot signal input 78.67 kHz, 0% modulation Only SAP carrier input Sine wave input f: Noise BPF peak Sine wave input f: Noise BPF peak 300 Hz, 100% modulation Conditions MIN. 33 11 3.0 -5.5 2.5 17 3.3 20 1.0 450 450 400 420 450 -0.5 -0.5 -1.0 -1.5 -6.5 -0.5 -1.0 -1.0 -11.0 -1.2 -1.0 -0.5 TYP. 45 16 6.0 -4.0 4.0 23 4.8 30 2.0 500 500 500 470 500 0 0 -0.3 -0.5 -4.0 0 0 0 -7.0 -0.1 +0.4 +1.7 MAX. 60 21 9.0 -2.5 5.5 30 6.3 40 3.0 550 550 600 520 550 +0.5 +0.5 +0.5 +1.0 -1.5 +0.5 +0.5 +1.0 -3.0 +1.2 +2.0 +4.0 Unit mA mVrms dB % % mVrms dB mVrms dB mVrms mVrms mVrms mVrms mVrms dB dB dB dB dB dB dB dB dB dB dB dB
Monaural total frequency characteristics 1 VOMO1 Monaural total frequency characteristics 2 VOMO2 Monaural total frequency characteristics 3 VOMO3 Monaural total frequency characteristics 4 VOMO4 Stereo total frequency characteristics 1 Stereo total frequency characteristics 2 Stereo total frequency characteristics 3 Stereo total frequency characteristics 4 SAP total frequency characteristics 1 SAP total frequency characteristics 2 SAP total frequency characteristics 3 VOST1 VOST2 VOST3 VOST4 VOSAP11 VOSAP12 VOSAP13
Data Sheet S12816EJ3V0DS00
35
PC1854A
(2/2)
Parameter SAP single frequency characteristics 1 Symbol VOSAP21 Conditions 1 kHz, 30% modulation (300 Hz: 0 dB) Noise reduction: OFF 3 kHz, 30% modulation (300 Hz: 0 dB) Noise reduction: OFF 8 kHz, 30% modulation (300 Hz: 0 dB) Noise reduction: OFF 300 Hz, 30% modulation 1 kHz, 30% modulation 3 kHz, 30% modulation 1 kHz, 100% modulation 1 kHz, 100% modulation 8 kHz, 30% modulation with DIN/AUDIO filter used 1 kHz, 100% modulation 1 kHz, 100% modulation Noise reduction: OFF 1 kHz, 100% modulation Monaural signal SAP: f = 3 kHz, 30% modulation Stereo: L-only, f = 800 Hz, 30% modulation SAP: f = 800 Hz, 30% modulation Stereo: L-only, f = 3 kHz, 30% modulation 300 Hz, 100% modulation Pre-emphasis: ON 300 Hz, 100% modulation Noise reduction: ON Signal: 300 Hz, 100% modulation Monaural signal 1 kHz, 100% modulation STI- and WTI-pin current flow Mute Monaural, no signal Mute Stereo, only pilot signal input Mute SAP1, only 5 fH signal input Mute Monaural (Normal output) Mute External SAP (Normal output) MIN. -0.5 TYP. 0 MAX. +0.5 Unit dB
SAP single frequency characteristics 2
VOSAP22
-0.5
0
+0.5
dB
SAP single frequency characteristics 3
VOSAP23
-1.0
0
+1.0
dB
Stereo channel separation 1 Stereo channel separation 2 Stereo channel separation 3 Monaural total harmonic distortion Stereo total harmonic distortion 1 Stereo total harmonic distortion 2 SAP total harmonic distortion SAP single harmonic distortion Normal output harmonic distortion Crosstalk 1 (SAP Stereo)
Sep1 Sep2 Sep3 THDMO THDST1 THDST2 THDSAP1 THDSAP2 THDNO CT1
27 25 27 -- -- -- -- -- -- --
32 30 35 0.1 0.3 0.8 0.5 0.7 0.1 -60
-- -- -- 0.5 1.5 1.8 2.0 2.0 0.5 -50
dB dB dB % % % % % % dB
Crosstalk 2 (Stereo SAP)
CT2
--
-60
-50
dB
Monaural total S/N Stereo total S/N SAP total S/N Normal output S/N Total muting level dbx timing current Inter-mode DC offset 1 Inter-mode DC offset 2 Inter-mode DC offset 3 Inter-mode DC offset 4 Inter-mode DC offset 5
S/NMO S/NST S/NSAP S/NNO Mute IT VDOF1 VDOF2 VDOF3 VDOF4 VDOF5
65 65 70 65 60 7.1 -50 -50 -50 -50 -50
68 68 80 68 70 7.5 0 0 0 0 0
-- -- -- -- -- 7.9 +50 +50 +50 +50 +50
dB dB dB dB dB
A
mV mV mV mV mV
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Data Sheet S12816EJ3V0DS00
PC1854A
Test Condition Parameters for Electrical Characteristics (Unless otherwise specified, TA = 25C, RH 70 %, VCC = 9 V) (1/7)
Parameter Supply current Stereo detection input sensitivity Stereo detection hysteresis Symbol ICC STSENCE STHY Test Conditions ICC : Current sent to VCC pin when there is no signal STSENCE : Input signal level of COM pin (input signal: 15.734 kHz) Read register D6 : when changed from 0 to 1 STHY =20 log (STSENCE / V) STSENCE : Stereo detection input sensitivity V : Input signal level of COM pin (Input signal: 15.734 kHz) Read register D6 : First set to 1, then changed to 0 by gradually lowering input signal level. STCCL = f / 15.734 kHz f : Difference between f and 15.734 kHz f : With signal (14.5 kHz, 30 mVrms) input to COM pin; The frequency, which is gradually raised and measured when read register D6 becomes 1 STCCH = f / 15.734 kHz f : Difference between f and 15.734 kHz f : With signal (17.0 kHz, 30 mVrms) input to COM pin; The frequency, which is gradually lowered and measured when read register D6 becomes 1 SAPSENCE : Input signal level of COM pin (input signal: 78.67 kHz) Read register D5 : when changed from 0 to 1 SAPHY =20 log (SAPSENCE / V) SAPSENCE : SAP detection input sensitivity V: Input signal level of COM pin (Input signal: 78.67 kHz) Read register D5 : First set to 1, then changed to 0 by gradually lowering input signal level. NOSENCE : Input signal level of COM pin Read register D4 : Changed to 0 by applying 6-V DC voltage to SDT pin. Read register D4 : With signal (160 kHz, 10 mVrms) input to COM pin; Changed to 1 by raising the frequency until the DC voltage of the NDT pin reaches the maximum level and, with maintaining this frequency, gradually raising the input signal level. NOHY = 20 log (NOSENCE / V) NOSENCE : Noise detection input sensitivity V: Input signal level of NDT pin COM pin : Signal (160 kHz, 90 mVrms) input Read register D4 : First set to 1, then changed to 0 by raising the frequency until the DC voltage of the NDT pin reaches the maximum level and, with maintaining this frequency, gradually raising the input signal level. VOMO : Output voltage of ROT and LOT pins COM pin: Monaural signal (300 Hz, 100% modulation) input Monaural SAP User ModeNote Monaural Stereo
Stereo detection capture range
STCCL
STCCH
SAP detection input sensitivity SAP detection hysteresis
SAPSENCE SAPHY
Noise detection input sensitivity
NOSENCE
Noise detection hysteresis
NOHY
Monaural total output voltage VOMO
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
37
PC1854A
(2/7)
Parameter Stereo total output voltage Symbol VOST Test Conditions User ModeNote
L-channel Stereo VOST : Output voltage of LOT pin COM pin : Stereo signal (L-only, 300 Hz, 100% modulation) input R-channel VOST : Output voltage of ROT pin COM pin : Stereo signal (R-only, 300 Hz, 100% modulation) input VOSAP1 : Output voltage of ROT and LOT pins COM pin : SAP signal (300 Hz, 100% modulation) input VOSAP2 : Output voltage of SOT pin COM pin : SAP signal (300 Hz, 100% modulation, Noise reduction: OFF) input VONO : Output voltage of NOT pin COM pin : Monaural signal (300 Hz, 100% modulation) input VOLR = 20 log (VL / VR) VL : Output voltage of LOT pin COM pin : Monaural signal (300 Hz, 100% modulation) input VR : Output voltage of ROT pin COM pin : Monaural signal (300 Hz, 100% modulation) input VOMO1 = 20 log {V(1k) / V(300)} V(1k) : Output voltage of LOT pin COM pin : Monaural signal (1 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Monaural signal (300 Hz, 30% modulation) input VOMO2 = 20 log {V(3k) / V(300)} V(3k) : Output voltage of LOT pin COM pin : Monaural signal (3 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Monaural signal (300 Hz, 30% modulation) input VOMO3 = 20 log {V(8k) / V(300)} V(8k) : Output voltage of LOT pin COM pin : Monaural signal (8 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Monaural signal (300 Hz, 30% modulation) input VOMO4 = 20 log {V(12k) / V(300)} V(12k) : Output voltage of LOT pin COM pin : Monaural signal (12 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Monaural signal (300 Hz, 30% modulation) input VOST1 = 20 log {V(1k) / V(300)} V(1k) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 1 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input VOST2 = 20 log {V(3k) / V(300)} V(3k) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 3 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input Stereo SAP1 SAP
SAP total output voltage SAP single output voltage
VOSAP1 VOSAP2
Normal output voltage Difference between monaural L and R output voltage
VONO VOLR
Monaural
Monaural total frequency characteristics 1
VOMO1
Monaural total frequency characteristics 2
VOMO2
Monaural total frequency characteristics 3
VOMO3
Monaural total frequency characteristics 4
VOMO4
Stereo total frequency characteristics 1
VOST1
Stereo total frequency characteristics 2
VOST2
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
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Data Sheet S12816EJ3V0DS00
PC1854A
(3/7)
Parameter Stereo total frequency characteristics 3 Symbol VOST3 Test Conditions VOST3 = 20 log {V(8k) / V(300)} V(8k) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 8 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input VOST4 = 20 log {V(12k) / V(300)} V(12k) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 12 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input VOSAP11 = 20 log {V(1k) / V(300)} V(1k) : Output voltage of LOT pin COM pin : SAP signal (1 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : SAP signal (300 Hz, 30% modulation) input VOSAP12 = 20 log {V(3k) / V(300)} V(3k) : Output voltage of LOT pin COM pin : SAP signal (3 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : SAP signal (300 Hz, 30% modulation) input VOSAP13 = 20 log {V(8k) / V(300)} V(8k) : Output voltage of LOT pin COM pin : SAP signal (8 kHz, 30% modulation) input V(300) : Output voltage of LOT pin COM pin : SAP signal (300 Hz, 30% modulation) input VOSAP21 = 20 log {V(1k) / V(300)} V(1k) : Output voltage of SOT pin COM pin : SAP signal (1 kHz, 30% modulation, Noise reduction: OFF) input V(300) : Output voltage of SOT pin COM pin : SAP signal (300 Hz, 30% modulation, Noise reduction: OFF) input VOSAP22 = 20 log {V(3k) / V(300)} V(3k) : Output voltage of SOT pin COM pin : SAP signal (3 kHz, 30% modulation, Noise reduction: OFF) input V(300) : Output voltage of SOT pin COM pin : SAP signal (300 Hz, 30% modulation, Noise reduction: OFF) input VOSAP23 = 20 log {V(8k) / V(300)} V(8k) : Output voltage of SOT pin COM pin : SAP signal (8 kHz, 30% modulation, Noise reduction: OFF) input V(300) : Output voltage of SOT pin COM pin : SAP signal (300 Hz, 30% modulation, Noise reduction: OFF) input SAP SAP1 User ModeNote Stereo
Stereo total frequency characteristics 4
VOST4
SAP total frequency characteristics 1
VOSAP11
SAP total frequency characteristics 2
VOSAP12
SAP total frequency characteristics 3
VOSAP13
SAP single frequency characteristics 1
VOSAP21
SAP single frequency characteristics 2
VOSAP22
SAP single frequency characteristics 3
VOSAP23
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
39
PC1854A
(4/7)
Parameter Stereo channel separation 1 Symbol Sep1 Test Conditions L-channel Sep1 = 20 log (VL / VR) VL : Output voltage of LOT pin COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input VR : Output voltage of ROT pin COM pin : Stereo signal (L-only, 300 Hz, 30% modulation) input R-channel Sep1 = 20 log (VR / VL) VR : Output voltage of ROT pin COM pin : Stereo signal (R-only, 300 Hz, 30% modulation) input VL : Output voltage of LOT pin COM pin : Stereo signal (R-only, 300 Hz, 30% modulation) input (465Z manufactured by EIDEN Co., Ltd.) L-channel Sep2 = 20 log (VL / VR) VL : Output voltage of LOT pin COM pin : Stereo signal (L-only, 1 kHz, 30% modulation) input VR : Output voltage of ROT pin COM pin : Stereo signal (L-only, 1 kHz, 30% modulation) input R-channel Sep2 = 20 log (VR / VL) VR : Output voltage of ROT pin COM pin : Stereo signal (R-only, 1 kHz, 30% modulation) input VL : Output voltage of LOT pin COM pin : Stereo signal (R-only, 1 kHz, 30% modulation) input (465Z manufactured by EIDEN Co., Ltd.) L-channel Sep3 = 20 log (VL / VR) VL : Output voltage of LOT pin COM pin : Stereo signal (L-only, 3 kHz, 30% modulation) input VR : Output voltage of ROT pin COM pin : Stereo signal (L-only, 3 kHz, 30% modulation) input R-channel Sep3 = 20 log (VR / VL) VR : Output voltage of ROT pin COM pin : Stereo signal (R-only, 3 kHz, 30% modulation) input VL : Output voltage of LOT pin COM pin : Stereo signal (R-only, 3 kHz, 30% modulation) input (465Z manufactured by EIDEN Co., Ltd.) Monaural total harmonic distortion Stereo total harmonic distortion 1 THDMO THDST1 THDMO : Distortion rate of LOT and ROT pins COM pin : Monaural signal (1 kHz, 100% modulation) input L-channel THDST1 : Distortion rate of LOT pin COM pin : Stereo signal (L-only, 1 kHz, 100% modulation) input R-channel THDST1 : Distortion rate of ROT pin COM pin : Stereo signal (R-only, 1 kHz, 100% modulation) input Monaural Stereo User ModeNote Stereo
Stereo channel separation 2
Sep2
Stereo channel separation 3
Sep3
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
40
Data Sheet S12816EJ3V0DS00
PC1854A
(5/7)
Parameter Stereo total harmonic distortion 2 Symbol THDST2 Test Conditions L-channel THDST2 : Distortion rate of LOT pin COM pin : Stereo signal (L-only, 8 kHz, 30% modulation) input R-channel THDST2 : Distortion rate of ROT pin COM pin : Stereo signal (R-only, 8 kHz, 30% modulation) input THDSAP1 : Distortion rate of LOT and ROT pins COM pin : SAP signal (1 kHz, 100% modulation) input THDSAP2 : Distortion rate of SOT pin COM pin : SAP signal (1 kHz, 100% modulation, Noise reduction off) input THDNO : Distortion rate of NOT pin COM pin : Monaural signal (1 kHz, 100% modulation) input User ModeNote Stereo
SAP total harmonic distortion THDSAP1 SAP single harmonic distortion Normal output harmonic distortion Crosstalk 1 (SAP stereo) THDSAP2
SAP1 SAP
THDNO CT1
Monaural
CT1 = 20 log (VCT1 / VL) Stereo VCT1 : VL after BPF (3 kHz) VL : Output voltage of LOT pin COM pin : Composite signal {Stereo signal (L-only, 800 Hz, 30% modulation) and SAP signal (3 kHz, 30 % modulation) } input BPF : Attenuation of 0 dB at 3 kHz and 80 dB at 800 Hz, or more CT2 = 20 log (VCT2 / VL) SAP1 VCT2 : VL after BPF (3 kHz) VL : Output voltage of LOT pin COM pin : Composite signal {SAPsignal (800 Hz, 30% modulation) and Stereo signal (L-only, 3 kHz, 30 % modulation) } input BPF : Attenuation of 0 dB at 3 kHz and 80 dB at 800 Hz, or more L-channel S/NMO = 20 log (VOMOL / VL) VOMOL : Output voltage of LOT pin COM pin : Monaural signal (300 Hz, 100% modulation) input VL : Output voltage of LOT pin (no signal) R-channel S/NMO = 20 log (VOMOR / VR) VOMOR: Output voltage of ROT pin COM pin : Monaural signal (300 Hz, 100% modulation) input VR : Output voltage of ROT pin (no signal) Monaural
Crosstalk 2 (stereo SAP)
CT2
Monaural total S/N
S/NMO
Stereo total S/N
S/NST
L-channel Stereo S/NST = 20 log (VOSTL / VL) VOSTL : Output voltage of LOT pin COM pin : Stereo signal (L-only, 300 Hz, 100% modulation) input VL : Output voltage of LOT pin COM pin : Pilot signal input R-channel S/NST = 20 log (VOSTR / VR) VOSTR : Output voltage of ROT pin COM pin : Stereo signal (R-only, 300 Hz, 100% modulation) input VR : Output voltage of ROT pin COM pin : Pilot signal input
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
41
PC1854A
(6/7)
Parameter SAP total S/N Symbol S/NSAP Test Conditions L-channel S/NSAP = 20 log (VOSAP1L / VL) VOSAP1L : Output voltage of LOT pin COM pin : SAP signal (300 Hz, 100% modulation) input VL : Output voltage of LOT pin COM pin : SAP carrier (0 % modulation) input R-channel S/NSAP = 20 log (VOSAP1R / VR) VOSAP1R : Output voltage of ROT pin COM pin : SAP signal (300 Hz, 100% modulation) input VR : Output voltage of ROT pin COM pin : SAP carrier (0 % modulation) input S/NNO = 20 log (VONO / VM) VONO : Output voltage of NOT pin COM pin : Monaural signal (300 Hz, 100% modulation) input VM : Output voltage of NOT pin (no signal) Mute = 20 log (VOMOL / VM) VOMOL : Output voltage of LOT pin COM pin : Monaural signal (300 Hz, 100% modulation) input VM : Output voltage of LOT pin Write register 06H, D0 : 0 COM pin : Monaural signal (300 Hz, 100% modulation) input IT : Current that flows from VCC to STI and WTI pins STI and WTI pins : 6-V DC is applied. VDOF1 = VMONO - VMute VMONO : DC voltage at LOT and ROT pins User mode : Monaural NDT pin : 6-V DC is applied. VMute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1 : 0) NDT pin : 6-V DC is applied. VDOF2 = VST - VMute VST : DC voltage at LOT and ROT pins User mode : Stereo NDT pin : 6-V DC is applied. VMute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1 : 0) NDT pin : 6-V DC is applied. VDOF3 = VSAP - VMute VSAP : DC voltage at LOT and ROT pins User mode : SAP1 NDT pin : 6-V DC is applied. VMute : DC voltage at LOT and ROT pins User mode : Mute (write register 06H, D1 : 0) NDT pin : 6-V DC is applied. Mute to Monaural User ModeNote SAP1
Normal output S/N
S/NNO
Monaural
Total muting level
Mute
Monaural mute
dbx timing current Inter-mode DC offset 1
IT VDOF1
Inter-mode DC offset 2
VDOF2
Mute to Stereo
Inter-mode DC offset 3
VDOF3
Mute to SAP1
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
42
Data Sheet S12816EJ3V0DS00
PC1854A
(7/7)
Parameter Inter-mode DC offset 4 Symbol VDOF4 Test Conditions VDOF4 = VMONO - VMute VMONO : DC voltage at NOT pin User mode : Monaural NDT pin : 6-V DC is applied. VMute : DC voltage at NOT pin User mode : Mute (write register 06H, D1: 0) NDT pin : 6-V DC is applied. VDOF5 = VEXT - VMute VEXT : DC voltage at NOT pin User mode : External SAP NDT pin: 6-V DC is applied. VMute : DC voltage at NOT pin User mode : Mute (write register 06H, D1 : 0) NDT pin: 6-V DC is applied. User ModeNote Mute to Monaural
Inter-mode DC offset 5
VDOF5
Mute to External SAP
Note For details about the User Mode, refer to chapter 5. MODE MATRIX.
Data Sheet S12816EJ3V0DS00
43
PC1854A
8. MEASURING CIRCUIT
PC1854A
A 22 F +
1
VCC
MOA 28
1 F + 10 F + 10 F + 10 F + 1 F + 10 F + 3.3 F + 1.6 k 15 k
VCC
9V
2
VRE
LOT 27
3 0.1 F 4 1 k 5 4.7 F + + 1 F 6
Multiple Audio Signal Generator
Note 1
PD1
ROT 26
PD2
NOT 25
D1
VOA 24
D2
WTI 23
2.2 F + 0.1 F + 0.047 F
7
COM
STI 22
Buffer
8
SOA
ITI 21 5.1 k 1 F + 3 k 1 F + 1 F +
Note 2 Filter
9 + 6V V 10 F + 0.47 F 68 k
SDT
WRB 20
Measuring Device A 6V DGND
10 NDT
SRB 19
11 SOT 0.1 F 12 SI
dO 18
DGND 17
13 ESA
SCL 16 I2C Bus Data
14 AGND
SDA 15
Notes 1. 465Z manufactured by EIDEN Co., Ltd. 2. 30 kHz LPF, DIN/AUDIO filter, or 3kHz BPF Remark Use the following for external parts. Resistor : Metal film resistor (1 %) for an ITI pin. Unless otherwise specified; 5 % Capacitor : Tantalum capacitor (10 %) for STI and WTI pins. Unless otherwise specified; 20 %
44
Data Sheet S12816EJ3V0DS00
PC1854A
9. PACKAGE DRAWINGS
28-PIN PLASTIC SDIP (10.16mm400))
28 15
1 A
14
J I
K L
F D H G
NOTES 1. Each lead centerline is located within 0.17 mm of its true position (T.P.) at maximum material condition. 2. Item "K" to center of leads when formed parallel.
ITEM A B C D F G H I J K L M N R MILLIMETERS 28.46 MAX. 2.67 MAX. 1.778 (T.P.) 0.500.10 0.85 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 10.16 (T.P.) 8.6 0.25 +0.10 -0.05 0.17 015 S28C-70-400B-2
N
M
M C B
R
Data Sheet S12816EJ3V0DS00
45
PC1854A
28-PIN PLASTIC SOP (9.53 mm (375))
28 15
detail of lead end
R 1 A 14
H F G S C D E M
M
I
J
B K
L N S
NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D E F G H I J K L M N R
MILLIMETERS 17.90.2 0.845 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.1250.075 2.9 MAX. 2.500.2 10.30.2 7.20.2 1.60.2 0.17 +0.08 -0.07 0.8 0.12 0.10 3 +7 -3 P28GT-50-375B-3
46
Data Sheet S12816EJ3V0DS00
PC1854A
10. RECOMMENDED SOLDERING CONDITIONS
The PC1854A should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 10-1. Surface Mounting Type Soldering Conditions
PC1854AGT : 28-pin plastic SOP (9.53 mm (400))
Soldering Method Infrared reflow VPS Wave soldering Partial heating Soldering Conditions Package peak temperature: 235C, Duration: 30 sec. max. (at 210C or above), Number of times: Three times max. Package peak temperature: 215C, Duration: 40 sec. max. (at 200C or above), Number of times: Three times max. Solder bath temperature: 260C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120C max. (Package surface temperature) Pin temperature: 300C max., Duration: 3 sec. max. (per pin row) Symbol IR35-00-3 VP15-00-3 WS60-00-1 --
Caution
Do not use different soldering methods together (except in the case of partial heating). Table 10-2. Inserting Type Soldering Conditions
PC1854ACT : 28-pin plastic SDIP (10.16 mm (400))
Soldering Method Wave soldering (only pins) Partial heating Soldering Conditions Solder bath temperature: 260C max., Duration: 10 sec. max. Pin temperature: 300C max., Duration: 3 sec. max. (per pin row)
Caution
Apply wave soldering only to the pins and be careful not to bring solder into direct contact with the package.
Data Sheet S12816EJ3V0DS00
47
PC1854A
Purchase of NEC I2C components conveys a license under the Philips I 2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
* The information in this document is current as of May, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. * NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).
M8E 00. 4

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